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Data bus test
#1
Download: ROM + source code

This is another test I've written that demonstrates the impact of utilizing memory in different ways.
The results will be printed in green if they match what I get on my NGPC +/- 1, and in red otherwise. Mednafen and NeoPop aren't even close.

Here are the correct results:
[Image: ngp_bus.jpg]

Each test begins by syncing against timer0, and then starting the actual
test, which consists of a loop that increments a counter once every 50
states. This loop is allowed to run for approximately 12800 states, at which
point it will be aborted by the timer interrupt, and the value of the counter
is printed.

Two hexadecimal values are printed at each row. The first value shows the result
when using good code alignment for the TLCS-900/H, and the second value shows
the result when using poor code alignment.

Brief explanation of what each sub-test means:

ROM
The code is executed from ROM, and only performs register-internal operations, so
no memory access is done execpt for instruction fetching.

RAM
Same as the above, except that the code is executed from RAM, which makes code alignment
relevant since you want to avoid unaligned memory accesses on the 16-bit bus.

ROM+ROM
Executes from ROM, and does 32-bit reads from ROM.

RAM+ROM
Executes from RAM, and does 32-bit reads from ROM.

RAM+RAM
Executes from RAM, and does 32-bit reads from RAM.

T+Z TTS
The TLCS-900/H and Z80 are executing at the same time.
The TLCS-900/H executes from non-shared RAM ("TLCS" RAM) and does 32-bit reads from non-shared
RAM. The Z80 executes from and writes to shared RAM.
The line that says "Z80" shows the counter value obtained on the Z80 side, while the line that
says "TLCS" shows the counter value obtained on the TLCS-900/H side.

T+Z SSS
The TLCS-900/H and Z80 are executing at the same time.
The TLCS-900/H executes from shared RAM and does 32-bit reads from shared RAM.
The Z80 executes from and writes to shared RAM.

T+Z TSS
The TLCS-900/H and Z80 are executing at the same time.
The TLCS-900/H executes from non-shared RAM and does 32-bit reads from shared RAM.
The Z80 executes from and writes to shared RAM.

T+Z STS
The TLCS-900/H and Z80 are executing at the same time.
The TLCS-900/H executes from shared RAM and does 32-bit reads from non-shared RAM.
The Z80 executes from and writes to shared RAM.

T+Z R S
The TLCS-900/H and Z80 are executing at the same time.
The TLCS-900/H executes from ROM.
The Z80 executes from and writes to shared RAM.
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Messages In This Thread
Data bus test - by mic_ - 10-20-2012, 11:06 PM
RE: Data bus test - by jdg - 10-24-2012, 05:15 AM
RE: Data bus test - by Cthulhu32 - 10-26-2012, 12:48 AM
RE: Data bus test - by mic_ - 10-26-2012, 03:26 AM
RE: Data bus test - by Cthulhu32 - 10-26-2012, 03:49 AM
RE: Data bus test - by mic_ - 10-26-2012, 05:24 AM
RE: Data bus test - by Flavor - 10-27-2012, 05:41 AM
RE: Data bus test - by mic_ - 10-27-2012, 07:09 PM

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